The present invention generally relates to the formation of vertical, shallow, and lightly doped, junctions for a vertical transistor, and more particularly to an improved method/structure that makes it possible to process a buried contact with reduced outdiffusion while still maintaining sufficient overlap between the buried contact and the transistor channel.
With further shrinking of groundrules for logic and dynamic random access memory (DRAM) devices, development of improvements becomes necessary. In case of planar logic and DRAM devices, short channel effects limit device performance. For DRAMs with vertical access transistor, the buried contact outdiffusion has to be reduced for isolation reasons, but connectivity to the select transistor must be assured. The invention described below processes a shallow buried contact by reducing the outdiffusion without degrading the connectivity to the select transistor.
The invention provides a trench storage structure that includes a substrate having a trench, a capacitor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the conductive strap, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an optional undoped trench top oxide layer above the doped trench top oxide layer.
The dopant in the doped trench top oxide layer comprises the same type of dopant in the conductive buried strap. A percentage by weight of dopant in the doped trench top oxide layer is less than 1%. The structure also includes a gate conductor in the trench above the undoped trench top oxide layer. The trench top oxide layer insulates the gate conductor from the capacitor conductor.
The invention also provides a method of forming a memory device that patterns a trench, forms the capacitor dielectric, fills the lower portion of the trench with a capacitor conductor, deposits a conductive node strap in the trench above the capacitor conductor, forms a trench top oxide in the trench adjacent the top of the conductive strap, and heats the structure to form a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide is formed by depositing a doped trench top oxide layer above the conductive strap, and forming an optional undoped trench top oxide layer above the doped trench top oxide layer.
The process of depositing the doped trench top oxide layer comprises a high density plasma-chemical vapor deposition (HDP-CVD) process that includes the following parameters: silane reactant gas flow 10-75 sccm; approximate bias plasma power 300-1000 W; and phosphine gas delivery at gas flows below 5 sccm. This processing forms the percentage by weight of dopant in the doped trench top oxide layer to be less than 1%.
To further shrink the vertical DRAM cell, with the invention, the lateral outdiffusion of the buried strap is reduced to avoid interaction between adjacent DRAM cells, while still maintaining a low resistive path to the channel region of the vertical transistor. By reducing the thermal budget of the entire process, the invention outdiffuses dopant from the doped TTO layer and reduces the outdiffusion of the buried strap. Thus, both lateral and vertical outdiffusions are reduced. Sufficient overlap between the buried strap and the transistor channel is not assured with conventional processes that only rely upon outdiffusion from the trench conductor and the node strap to form the buried strap. This is why a portion of the TTO is doped in the inventive structure. In addition, the inventive HDP-CVD TTO deposition process was developed to provide good dopant control in the oxide, to consistently achieve this structure.